1. Field of the Invention
The present invention relates to a solid state imaging device comprising an AD converter for each of columns in a pixel array unit where unit pixels each including a photoelectric conversion element are two-dimensionally arrayed in a matrix shape, and a method of driving the solid state imaging device. The technology according to the present invention is particularly suitable for the improvement of the dynamic range.
2. Description of the Related Art
In recent years, a CMOS image sensor provided with a column parallel ADC in which an AD converter is provided in each of columns in a pixel array unit has been developed as a solid state imaging device. The structure of the CMOS image sensor is recited in, for example, No. 2006-33452 of the Japanese Patent Applications Laid-Open.
FIG. 11 is a block diagram illustrating a constitution of a conventional solid state imaging device B. In FIG. 11, 10 denotes a pixel array unit where unit pixels 12 each including a photoelectric conversion element are two-dimensionally arrayed in a matrix shape, 14 denotes a row selecting wire, 16 denotes a column signal wire, 18 denotes a row scanning circuit, and 20 denotes a column AD converter provided with a plurality of analog CDSs (CDS: correlated double sampling) 22 provided for each column and an array of a plurality of AD converters 24 provided for each column. The AD converter 24 comprises a comparator 26 and an up-down counter 28. 30 denotes a line memory which is an array of a plurality of memory cells 32 provided for each column, where an AD conversion result by the AD converter 24 provided for column is temporarily stored. 40 denotes a column scanning circuit, 50 denotes a timing control circuit, 60 denotes a DA converter which generates a reference voltage Vr having a ramp waveform (a waveform having a slope shape).
The unit pixels 12 are arrayed in the two-dimensional matrix shape in the pixel array unit 10, and the unit pixels 12 for one row are respectively connected to the row scanning circuit 18 via the row selecting wires 14. Further, the unit pixels 12 for one column are respectively connected to input terminals of the analog CDS 22 for column in the column AD converter 20 via the column signal wires 16. The output terminal of the analog CDS 22 for each column is connected to one of the two input terminals of the comparator 26 in the AD converter 24 for each column, the output terminal of the DA converter 60 is connected to the other input terminal of the comparator 26, and the output terminal of the comparator 26 is connected to the input terminal of the up-down counter 28.
The reference voltage Vr having a ramp waveform is supplied to the comparators 26 from the DA converter 60, and a pixel signal voltage Vx is outputted from each of the unit pixels 12 via the column signal wire 16 and the analog CDS 22. The comparator 26 compares the pixel signal voltage Vx to the reference voltage Vr having the ramp waveform, and inverts a comparison result Vc when a comparison result shows that the two voltages are equal to each other. The AD conversion is performed through the cooperation of the comparator 26 and the up-down counter 28. The up-down counter 28 has an additional function of temporarily retaining a count value obtained and adding the retained count value to a count value subsequently obtained.
Output terminals of the up-down counters 28 for each column are connected to the memory cells 32 in the line memory 30, and data written in the memory cells 32 after the completion of the AD conversion is sequentially outputted by the column-scan operation by the column scanning circuit 40. The timing control circuit 50 timing-controls the row scanning circuit 18, column AD converter 20, DA converter 60, line memory 30 and column scanning circuit 40.
Next, an operation of the conventional solid state imaging device B thus constituted is described. The description relates to a device driving example in a case where digital double sampling is performed. FIG. 12 is a timing chart illustrating the operation in the foregoing case.
1) First, a counting operation in a first sampling process is described referring to the first-half part of FIG. 12. In the first sampling, a baseline voltage Vt is a judgment target. At that time, the timing control circuit 50 indicates a down count mode to the up-down counters 28, and the up-down counters 28 correspondingly perform down count. In the unit pixels 12 in the row selected by the row scanning circuit 18, the baseline voltage Vt generated in each pixel in the relevant row (corresponding to reset component) is inputted to the comparator 26 via the analog CDS 22. The comparator 26 compares the baseline voltage Vt to the reference voltage Vr (ramp waveform) from the DA converter 60. During the operation described above, the up-down counters 28 continue to down-count the reference clocks. When the reference voltage Vr (ramp waveform) exceeds the baseline voltages Vt, the comparison results Vc outputted from the comparators 26 are inverted to “H” level. The up-down counters 28 halt their counting operations in response to the inversion, and retain count values CNT obtained then as reset components ΔD. Accordingly, the count values CNT additionally include the reset components ΔD in the up-down counters 28. The reset components ΔD correspond to the reference voltages Vt. Because the count values CNT additionally include the reset components ΔD, an inter-pixel variability of offset voltages at the time of no signals is resolved. The reset components ΔD are temporarily retained in the up-down counters 28. When the generation of the reference voltage Vr is halted after a first predetermined time passed, the comparison results Vc return to “L” level.
2) After a second predetermined time (second predetermined time>first predetermined time) has passed, the up-down counters 28 shift to a second sampling process, which is described referring to the latter-half part of FIG. 12. In the second sampling, the pixel signal voltage Vx is the judgment target. At that time, the timing control circuit 50 indicates an up count mode to the up-down counters 28, and the up-down counters 28 correspondingly perform up-count. Analog signals generated at each pixel in the respective unit pixels 12 in the row selected by the row scanning circuit 18 are noise-removed by the respective analog CDSs 22 and inputted to the comparators 26 as the pixel signal voltages Vx. The comparators 26 compare the pixel signal voltages Vx to the reference voltage Vr (ramp waveform) from the DA converter 60. During that operation, the up-down counters 28 continue to up-count the reference clocks. In the counting operations by the up-down counters 28 at the time, the reset components Δ D obtained in the down-counting operation are used as initial values.
When the reference voltage Vr exceeds the pixel signal voltages Vx, the comparison results Vc outputted from the comparators 26 are inverted to “H” level. The up-down counters 28 halt their counting operations in response to the inversion and retain the count values CNT obtained at the time. The count value CNT additionally includes the reset component ΔD obtained in the down-counting. Therefore, a digital pixel value of a regular signal component corresponding to the pixel signal voltage Vx is Dx. In the digital pixel value Dx, the inter-pixel variability is resolved since the reset component is removed therefrom. The digital pixel values Dx are temporarily retained in the respective up-down counters 28. Accordingly, the AD conversion for one pixel is completed, and the obtained digital pixel values Dx are transferred to the memory cells 32 in the respective columns in the line memory 30. The digital pixel value Dx thus generated correspond to a counting period Tx from the start to the halt of the counting operation by the down-counter 28.
The signal processing for each column thus described is executed at once at all of the unit pixels 12 in the selected row in the pixel array unit 10. More specifically, the analog CDSs 22, comparator 26, up-down counters 28 and memory cells 32 in the respective columns are operated in a manner similar to the operation described above, and the digital pixel values Dx corresponding to the analog signals obtained from all of the unit pixels 12 in the selected row are retained in the memory cells 32. Then, the column scanning circuit 40 column-scans the memory cells 32 of the line memory 30, and sequentially outputs pixel data of one selected row outside.
The row to be selected is repeatedly updated by the row scanning circuit 18 so that the pixel signal processing for one selected row described above is executed for all of the selected rows. As a result, digital pixel data for one field can be obtained.
The conventional technology thus described wherein the linearity variability and saturation variability between the pixels are not taken into account in characteristic curves based on light intensity—signal level, is, however, disadvantageous in that the S/N ratio is lowered, which deteriorates an image quality. Below is described the disadvantage. FIG. 13 shows a relationship between an incident light intensity and a signal level resulting from photoelectric conversion (characteristic curves based on light intensity—signal level) in a photoelectric conversion element of the unit pixel 12 in the pixel array unit 10. The signal level is proportional to the light intensity; however, the inter-pixel variability is generated in the linearity and saturation of the signal level when the light intensity exceeds a certain level.
In the description of the operation referring to FIG. 12, the baseline voltage Vt to be judged is substantially below a variability range B of the saturation of the light intensity—signal level in the first sampling. Therefore, the operation is limited to the region where the linearity of the baseline voltage Vt is retained, and the reference voltage Vr can maintain an enough accuracy as an index for judging the baseline voltage Vt. In the case where the pixel signal voltage Vx is below the variability range B in the second sampling, the reference voltage Vr can maintain an enough accuracy as an index for judging the pixel signal voltage Vx in a similar manner. When the pixel signal voltage Vx is within the variability range B, however, the accuracy of the reference voltage Vr as the index for judging the pixel signal voltage Vx is lessened.
Referring to FIG. 14 is given a further description. In a state where the level of the pixel signal voltage Vx is Vx1 which is the lowest level in the variability range B, the counting period is T11, and the digital pixel value Dx is D11. In a state where the level of the pixel signal voltage Vx is V x2 which is an intermediate level in the variability range B, the counting period is T12, and the digital pixel value Dx is D12. In a state where the level of the pixel signal voltage Vx is Vx3 which is the highest level in the variability range B, the counting period is T13, and the digital pixel value Dx is D13. When the level of the pixel signal voltage Vx is thus high and falls within the variability range B, the digital pixel value Dx largely varies. In the case where the level of the pixel signal voltage Vx is within the variability range B, the inter-pixel variability in the characteristic curves based on light intensity—signal level is directly shown in an image signal, resulting in the deterioration of an S/N ratio.
No. 2006-33454 of the Japanese Patent Applications Laid-Open recites the technology for extending the dynamic range by combining long-time and short-time exposure signals. According to the technology, the down-counting and up-counting operations are combined in the sampling process, so that the operation is applicable to both of the long-time exposure signal and short-time exposure signal, as shown in FIG. 15. More specifically, the down-counting and up-counting operations are performed during the detection of the long-time exposure signal, and then, the down-counting and up-counting operations are also performed during the detection of the short-time exposure signal. When the detection of the long-time exposure signal is shifted to the detection of the short-time exposure signal, a memory of the up-down counters 28 are not reset. The down-counting operation (long-time exposure) is performed, the up-counting operation (long-time exposure) is performed, and then, without the reset, the down-counting operation (short-time exposure) and the up-counting operation (short-time exposure) are performed again. Accordingly, a digital pixel value of the long-time exposure signal and a digital pixel value of the short-time exposure signal are combined by the up-down counters 28. As a result of the combination of the long-time and short-time exposure signals, the dynamic range is extended.
Because it takes a long exposure time to obtain a long-time exposure signal, the long-time exposure signal tends to fall within in the inter-pixel variability range B in the characteristic curves based on light intensity—signal level. In that case, an S/N ratio is deteriorated due to the variability of the digital pixel value Dx1; therefore, the image quality is significantly deteriorated though the dynamic range can be extended. Further, in the case where signals having the different exposure times are thus combined in a sensor, it is difficult to reduce the generated variability after the signals are outputted from the sensor.